FPGA Verification Engineer

Piper Companies is seeking an FPGA Verification Engineer to work onsite in San Jose, CA five days per week. The FPGA Verification Engineer  will ensure the robustness and seamless operation of a cutting-edge digital design environment for FPGA development, utilizing Verilog and UVM.

Responsibilities of the FPGA Verification Engineer include:

• Design and implement object-oriented testbench infrastructure, including Bus Functional Models (BFMs) and test cases, using UVM.
• Collaborative Debugging: Work closely with RTL designers to identify and resolve design issues.
• Independently create detailed test plans, develop test sequences, and generate stimuli to ensure robust verification.
• Utilize industry-standard tools and scripting languages to streamline and enhance verification processes.

Qualifications for the FPGA Verification Engineer include:

• 5-8 years of verification experience in FPGA and ASIC environments.
• Eligible to work in the U.S. and able to obtain and maintain an Active U.S. Government Secret Clearance.
• Proficient in SystemVerilog and object-oriented programming principles.
• Experience in developing testbench infrastructure, BFMs, and test cases using UVM.
• Bachelor's Degree in Electrical Engineering required; Master's degree preferred.
• Must work onsite 5 days a week in San Jose, CA.
• Must be eligible to work in the United States and able to obtain and maintain an Active U.S. Government Secret Clearance.

Compensation for the FPGA Verification Engineer include:

• $140,000 - $165,000
• Comprehensive benefit package: Medical, Dental, Vision, 401k match plus PTO, and Sick Leave if required by law

This job opens for applications on March 28th, 2025. Applications for this job will be accepted for at least 30 days from the posting date.

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