Packet Processor Architect

Piper Companies is hiring an Packet Processor Architect with a small start up based in Saratoga, CA. The Packet Processor Architect will help define Eridu’s next-gen networking ASICs built for AI infrastructure, working closely with the CTO and top-tier designers in an intensive, collaborative environment.. The Packet Processor Architect will need to sit on site in Saratoga, CA 5 days per week.

Responsibilities of the Packet Processor Architect:

• Architect L2–L4 packet processing pipelines: ingress/egress, classification, ACLs, parsing/deparsing, and tunneling protocols (VXLAN, GRE, IPinIP)
• Design lookup engines, table management, hash structures, and metadata handling
• Define parsing, packet editing, and scheduling capabilities
• Translate system-level goals into detailed architecture specs
• Collaborate with RTL, firmware, and physical design teams
• Validate architecture via modeling and performance analysis
• Guide integration of IP blocks (e.g., TCAM, SerDes, PCIe, DMA)
• Support post-silicon bring-up, debug, and tuning
• Participate in design reviews and architecture methodology definition

Requirements for the Packet Processor Architect:

• MSEE or equivalent with 15+ years in networking/datapath ASICs
• Proven background with switch/router ASICs (e.g., Cisco Silicon One, Marvell)
• Deep experience in packet processors and programmable pipelines
• Familiar with protocols like BGP, VXLAN, IPv6 Segment Routing (bonus for multiple)
• Strong in architecture modeling, performance tuning, and debugging
• Comfortable with intensive on-site collaboration

Compensation for the Packet Processor Architect:

• $280,000-$300,000
• Comprehensive Benefits: Health, Vision, Dental, PTO, Paid Holiday, Sick Leave if Required by Law

Keywords: packet processor architect, networking ASIC, switch ASIC, router ASIC, Cisco Silicon One, Marvell, packet processing pipeline, ingress processing, egress processing, routing, switching, forwarding engine, lookup tables, hash tables, lookup engine optimization, parser, deparser, ACL, QoS, congestion control, metadata handling, tunnel protocols, VXLAN, BGP, IPv6 segment routing, microarchitecture, performance modeling, high-throughput architecture, table management, hardware scheduling, TCAM, PCIe, SerDes, DMA, RTL collaboration, post-silicon validation, AI networking, data center, hands-on architecture, San Jose

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This job opens for applications on 9/9/2025. Applications for this job will be accepted for at least 30 days from the posting date.