Senior Power Integrity Engineer

Piper Companies is seeking a Senior Power Integrity Engineer for a cutting-edge semiconductor and hardware engineering organization. The Senior Power Integrity Engineer will focus on advanced power delivery network (PDN) design, end‑to‑end modeling, high‑speed package/PCB power architecture, and system‑level power integrity validation across complex chip and wafer‑scale platforms. This engineer will drive PDN design strategy, perform deep analytical simulations, and provide recommendations to ensure stable, efficient, and scalable power delivery in next‑generation products. This is a full-time onsite opportunity located in the San Jose area in California.

Responsibilities for the Senior Power Integrity Engineer include:

·      Design, analyze, and validate power delivery networks (PDNs) for highly integrated chips and wafer‑level systems.

·      Model and simulate power delivery paths from input source through pads, BGAs, routing layers, vias, and embedded capacitors. 

·      Perform detailed DC and AC power load analysis to characterize system requirements and performance.

·      Generate comprehensive technical outputs including end‑to‑end impedance plots, current density reports, and power plane evaluations.

·      Provide analysis‑based recommendations related to ballmaps, routing rules, stackup configurations, and power plane strategies.

·      Evaluate tradeoffs and performance impacts of various decoupling capacitor strategies.

·      Collaborate with cross‑functional engineering teams to ensure robust power integrity throughout the design cycle.

Qualifications for the Senior Power Integrity Engineer include:

·      10+ years of professional experience in power integrity analysis, PDN design, or related fields.

·      Developed PDN architectures for PCBs and organic substrates, including advanced multilayer stackups.

·      Working knowledge of vertical power delivery architectures and advanced PDN structures.

·      Hands‑on experience with power integrity modeling and simulation tools such as ADS, MATLAB, Q3D, SiWave, or equivalent.

·      Strong understanding of analog and digital circuit design principles.

·      Master’s degree or higher in Electrical Engineering.

Compensation for the Senior Power Integrity Engineer includes:

·      Salary range: $210,000 - $280,000

·      Comprehensive benefits package including Medical, Dental, Vision, 401k, PTO, holidays, and sick leave as required by law.

Keywords: Power Integrity, PI, Power Delivery Network, PDN, PDN design, PDN, analysis, vertical power delivery, power architecture, decoupling strategy, impedence modeling, current density analysis, power plane design, stackup optimization, ballmap, ADS, dvanced design system, MATLAB, Ansys Q3D, Ansys SiWave, HFSS, SPICE, cadence allegro, Xpedition, mentor graphics, PCB design, organic substrate design, BGA power delivery, high-speed packaging, CoWoS, 2,5D, 3D packaging, Flip-chip PDN, wafer-scale integration, analog circuit design, digital circuit design, EM/IR analysis, DC analysis

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This job is open for applications on 2/13/2026 and will remain open for at least 30 days from the posting date.